<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Rtos on Embedded Coffe</title><link>https://embeddedcoffe.my.id/tags/rtos/</link><description>Recent content in Rtos on Embedded Coffe</description><generator>Hugo</generator><language>en-US</language><lastBuildDate>Mon, 10 Aug 2026 14:30:00 +0000</lastBuildDate><atom:link href="https://embeddedcoffe.my.id/tags/rtos/index.xml" rel="self" type="application/rss+xml"/><item><title>Mastering FreeRTOS Task Scheduling on STM32</title><link>https://embeddedcoffe.my.id/posts/stm32-freertos-task-scheduling/</link><pubDate>Mon, 10 Aug 2026 14:30:00 +0000</pubDate><guid>https://embeddedcoffe.my.id/posts/stm32-freertos-task-scheduling/</guid><description>&lt;p&gt;When transitioning from a simple super-loop (&lt;code&gt;while(1)&lt;/code&gt;) architecture to a Real-Time Operating System (RTOS), understanding the scheduler&amp;rsquo;s behavior is vital for predictable and crash-free execution.&lt;/p&gt;
&lt;p&gt;In this article, we dissect how FreeRTOS manages task context switching on ARM Cortex-M4 cores (STM32F4/G4 series) and how to avoid classic concurrency pitfalls.&lt;/p&gt;
&lt;h2 id="the-cortex-m-pendsv-exception"&gt;The Cortex-M PendSV Exception&lt;/h2&gt;
&lt;p&gt;FreeRTOS relies on the &lt;strong&gt;PendSV&lt;/strong&gt; (Pended Service Call) exception to perform context switches safely. Unlike hardware ISRs that must execute with minimal latency, PendSV is configured with the lowest interrupt priority.&lt;/p&gt;</description></item></channel></rss>